Programmable logic devices (PLDs) typically comprise a plurality of logic units each configurable by data stored in associated configuration memories. In operation, data is transferred between logic elements via a routing network comprising a number of programmable interconnects joining the logic elements together. By transferring data between the logic units the programmable logic device is able to perform useful logic functions.
It is desirable for the routing between the logic units to operate at high speed so that the functions of the device can be performed efficiently. However, there are a number of problems to be overcome in order to implement high speed routing network designs.
A number of conventional techniques exist to increase the speed of routing networks which typically include the use of custom design techniques. For example, custom switches can be implemented comprising either nMOS only transistors or pass gates. One solution to providing a fast interconnection utilizing nMOS pass transistors is described in, for example, U.S. Pat. No. 7,570,079. It is well known to those skilled in the art that nMOS pass transistors are substantially faster than their pMOS equivalents, or complementary MOS logic (CMOS).
The performance of an application mapped to a PLD is determined by the worst delay for the longest path out of all of the paths in the application. If the worst delays in the longest paths of an application can be reduced, then the total performance for the application can increase.
In turn, a path in an application is composed of two separate types of elements: logic elements (LE-complex ALUs, look-up tables, etc) and routing network segments (RNS). These two differ in the fact that LEs may compute a logical function of one or more inputs (Z=A+B, Z=A|B, . . . ), whereas RNSs only transfer data without changing the logical function (Z=A). A typical path consists of alternate LEs and RNSs, and the delay(s) associated with the path are a combination of the delays for the LEs and the RNSs.
Typically each RNS is associated with two delays, one delay (rising) where the signal starts off from a low voltage and increases to a high voltage and one delay (falling) where the signal starts off from a high voltage and decreases to a low voltage. These delays are often different, so the longest one is likely to determine the application performance.
Standard application specific integrated circuit (ASIC) design techniques will try to optimise the two delays simultaneously, so that the difference between the worst delay and best delay is as small as possible.
Another technique effectively used by ASIC designers is logic pre-charging, as described, for instance, in U.S. Pat. No. 5,051,620. This technique can be used effectively in ASIC design but cannot be applied to PLDs due to the programmability of the device.